Multi-layer printed circuit board fabrication system and method

ABSTRACT

A method for aligning an image to be recorded by a direct image scanner on an upper layer of a printed circuit board with an image recorded on a lower layer thereof, the method comprising visually imaging a portion of the image on the lower layer and recording a pattern on the upper layer, referenced to coordinates of the visual image of the portion.

FIELD OF THE INVENTION

[0001] The present invention is related to the field of electricalcircuit fabrication and especially to the field of printed circuit boardfabrication employing a laser direct imaging device.

BACKGROUND OF THE INVENTION

[0002] It is known to manufacture printed circuit boards by way of aso-called sequentially build up methodology in which at least one outerlayer is sequentially added to an already existing printed circuit boardcore.

[0003] Systems for recording electrical circuit patterns on printedcircuit board substrates include exposure systems employing projectorsand phototool type mask having an image of an electrical circuit formedonto a transparent film.

[0004] PCT patent publication WO 00/02424, the disclosure of which isincorporated herein by reference, describes a scanning laser directimaging (LDI) system for writing an electric circuit pattern on aprinted circuit board substrate.

[0005]FIG. 1 is a reproduction of FIG. 1 of the above referencedpublication. Some details of its operation are given below. Furtherdetails of the operation and an explanation of the figure can be foundin the publication. In such systems, a laser beam or beams, modulatedwith pattern data, is scanned across a sensitized printed circuit boardsubstrate 78 to write a latent image of a desired electrical circuitpattern.

[0006] The substrate is optionally inverted and a second pattern in sideto side alignment with the first pattern is written on the other side ofthe substrate. In accordance with some printed circuit board fabricationtechniques, substrate layers may be sequentially laminated to previouslyproduced substrate layers and an electrical circuit pattern is writtenon the outermost side of each sequentially added layer in a build upfashion. The latent patterns are developed to form etching masks on thesubstrate. The masked substrate is etched to form the desired electricalcircuit pattern.

[0007] Among the problems which arise in printed circuit boardfabrication is the side to side alignment of printed circuit patterns onvarious substrate layers, and mutual alignment among patterns printed onvarious substrate layers. One method utilized to obtain suitablealignment is disclosed in the embodiment of FIGS. 1, 2, 14, 15 and 16,of the publication (FIG. 2 is a reproduction of FIG. 14 of the abovereferenced publication.). PC board substrate 78 is formed with aplurality of holes 150 at least some of which are preferably aligned, atleast roughly, in the scan direction. A base on which the substrate ismounted is formed with openings larger than the holes in the substrateand the holes in the substrate are positioned generally incorrespondence to the openings in the base. One or more detectors 152are positioned below the scan line of the scanner.

[0008] As the printed circuit board is transported past the scan line,the scanner scans across the holes in a substrate layer. Based onsignals detected by detector 150 via the holes and the openings, thelocations of the holes in the substrate layer with respect to thescanner are detected. The base is optionally rotated and scanning of theprinted circuit board substrate then commences with the position of thescanning lines pattern being referenced to the location of the holes.

[0009] It should be noted that the position of the scanning beam thatpasses through holes 150 is scanned together with another beam thatimpinges a scale 80 that is used to determine the true instantaneous(scan dimension) position of the beam in the scan direction.Furthermore, the relative cross-scan position of the holes (and thus theboard) is determined utilizing a second scale, typically operativelyassociated with the base.

[0010] When scanning the second side of the substrate, the procedure isrepeated to determine the position of the holes and thus the position ofthe already scanned pattern on the first side of the substrate (or theposition of already scanned patterns on lower layers in a build upboard) with respect to the coordinate space of the LDI system. Thisallows for the data in the scanning of each subsequent side to bealigned with respect to previously scanned sides.

[0011] Optionally, an additional series of holes in the board and pinson the base, or a guide rail along the base, may be used for roughalignment of the substrate. Such pins are shown in FIG. 16 of thereference. In some conventional systems, only such mechanical means areused for aligning the patterns on the two sides of the substrate. Thesystem may include means for rotating the board to improve alignment.

[0012] Measuring systems employing imagers, and especially CCD cameras,are known in the art for use in determining the positioning of a PCboard in an LDI scanner. Generally, such cameras may be used to detectvarious markings on a printed circuit board laminate layer, or to detectan edge of a printed circuit board laminate layer and to relate thedetected position of the marking or the edge with a scanner position.

SUMMARY OF THE INVENTION

[0013] An aspect of some embodiments of the invention is concerned withmethods of aligning to be written on a subsequent sequentially addedlayer (hereinafter the upper layer) which is overlaid on a PC board core(“the lower layer”) to images already written thereon.

[0014] In general, in sequential build-up an electrical circuit patternis first created by conventional means in the lower layer and then anupper layer is added. The upper layer contains a first dielectricmaterial, and a superimposed second layer of conducting material. Holesare created in the upper layer so as to enable creation of electricallyconductive paths between the upper and lower layers the conductingmaterial is coated, temporarily with a photoresist layer. The scannerthen writes a pattern on the photoresist aligned with the previouslycreated pattern on the lower layer. The photoresist is developed and theconductive material is etched, to providee the electrical pattern in theupper layer.

[0015] However, recording an image of a circuit pattern on the upperlayer which is aligned to patterns formed on upper and lower layers isnot trivial. Firstly, according to the method outlined above, the lowerlayer is covered by copper and any fiducial marks in the lower layer arenot visible. Second, even if fiducial marks are visible, they must beassociated with the position of the image to be written on the upperlayer.

[0016] Applicant's copending U.S. patent application Ser. No.09/708,160, filed Nov. 8, 2000, the disclosure of which is incorporatedherein by reference, describes methods and apparatus for aligning therespective coordinate systems of a scanner portion of a laser directimaging scanner and an imager, such as a camera, that views the printedcircuit board while it is mounted on the scanner. The substance of thisapplication is included the detailed description hereof.

[0017] While the methods of aligning the camera and apparatus forrecording an electrical circuit pattern on a substrate shown inApplicant's copending U.S. patent application Ser. No. 09/708,160comprise methods for performing such alignment, other methods ofalignment may also be used in the present invention.

[0018] In accordance with one embodiment of the invention, the positionsof marks formed on the lower layer are used to align the image beingrecorded on the upper layer with a pattern already formed on the lowerlayer. The marks may be made visible by forming openings in the upperlayer through which the alignment markings can be viewed by the camera.Alternatively, the upper layer may be formed without a copper coating inthe areas of the markings, for instance by masking those areas. Iftransparent or partially transparent dielectric materials are used forforming the upper layer, the markings can then be viewed by the imagingsystem and used for alignment of the image on the upper layer beingwritten by the scanner.

[0019] Alternatively, use is made of vias that are drilled in anaccurate position in the upper layer relative to a pattern on the lowerlayer to align the upper layer with the lower layer. In particular, asknown in the art of printed circuit board manufacture, micro-vias aredrilled on a micro-machining device which employs unveiled fiducialmarkings on a lower layer to drill the micro-vias in the upper layer insuitable alignment to the lower layer. Alternatively, themicro-machining device may use fiducial markings which are viewed withan x-ray imager, or holes drilled by a drilling including an x-rayimager, which holes are based on the internal conductive patterns theimager detects.

[0020] Still alternatively, use is made of a pattern that is producedwith reference to drilled via holes, or with reference to the part ofthe electrical circuit pattern formed on the lower layer.

[0021] In accordance with an embodiment of the invention, a hole patternor more usually a series of hole patterns, suitable for imaging, isdrilled in the upper layer, if a second build-up layer is superimposedon the first, or is drilled as through holes additionally passingthrough the lower layer or layers. When the board is placed on anexposure device, such as a laser direct imaging scanner scanner, torecord an image of a pattern on the upper layer, the holes are viewed bythe camera and are used to determine (utilizing, inter alia, thetransformation between the scanner and imaging coordinate systems) theappropriate location, and optionally scaling factor, for recording apattern on the upper layer such that the image to be recorded is alignedwith the holes.

[0022] In some embodiments of the invention, the hole patterns aredrilled in positions determined by local features of the lower layer.These features may include alignment patterns especially formed onto thelower board. Such patterns may be used to provide an overall shrinkagefactor to be applied to the board or to provide a full warping transformto the board. In writing upper board, the data is adjusted either on-thefly or by producing transformed data to fit the image to be written ontothe lower image.

[0023] Similarly, when the lower layer has a number of alignmentpatterns that are visible when the upper layer is in place, theplurality of patterns can be used to provide either an overall shrinkagecorrection (which may be different in the x and y directions) or a fullwarp correction.

[0024] There is thus provided, in accordance with a preferred embodimentof the invention, a method for aligning an image to be recorded by adirect image scanner on an upper layer of a printed circuit board withan image recorded on a lower layer thereof, the method comprising:

[0025] visually imaging a portion of the image on the lower layer; and

[0026] recording a pattern on the upper layer, referenced to coordinatesof the visual image of the portion.

[0027] In an embodiment of the invention, the portion is an alignmentpattern recorded on the lower layer. Optionally, the method comprisesforming an opening in the upper layer through which the alignmentpattern is visible. Optionally, the alignment pattern is visible throughthe upper layer.

[0028] In an embodiment of the invention recording includes providing anobject aligned with the image portion; and recording the pattern on theupper layer, referenced to the object. Optionally, the object comprisesholes formed in the upper layer. Optionally, the holes comprise holesthat do not pass through the lower layer. Optionally, the holes arevias. Optionally, the holes comprise functional vias connecting patternson the upper and lower layers. Optionally, where the images compriseelectrical circuits and wherein the holes are not related to anelectrical function of the printed circuit board. Optionally, the holespass through the upper and lower layers. Optionally, the holes form analignment pattern, referenced with the image on the lower layer.Optionally, the images comprise electrical circuits and wherein theholes are not related to an electrical function of the images.Optionally, the holes pass through the upper and lower layers.

[0029] In an embodiment of the invention, the method includes imagingthe object; and determining a position of the object, wherein thepattern is recorded relative to the determined position.

[0030] There is further provided, in accordance with an embodiment ofthe invention, a method for aligning an image to be recorded by a directimage scanner on an upper layer of a printed circuit board substratewith a pattern on a lower layer thereof, the method comprising:

[0031] detecting at least one hole provided in the upper layer, said atleast one hole being provided in predetermined alignment to said patternand said at least one hole not passing through said lower layer; and

[0032] scanning a pattern on the upper layer in predetermined alignmentwith said at least one hole.

[0033] There is further provided, in accordance with an embodiment ofthe invention, a method for recording an image on an upper layer of amulti-layered printed circuit board substrate, the method comprising:

[0034] forming at least one hole in an upper layer of a multi-layeredprinted circuit board substrate, said at least one hole having a knownspatial orientation to a pattern formed on one layer of the substrateand said substrate having at least two layers of circuitry alreadyformed thereon;

[0035] acquiring an image of the at least one hole;

[0036] calculating a location of the at least one hole from analysis ofthe image; and

[0037] recording a pattern on the upper layer with reference to saidlocation.

[0038] Optionally, forming at least one hole comprises forming at leastone hole with a laser micro-machining device. Optionally, forming atleast one hole comprises forming the at least one hole in at least theupper layer and not forming at least one hole in at least another layerof said multi-layered printed circuit board substrate. Optionally,acquiring an image includes acquiring a digital image of the at leastone hole. Optionally, calculating a location of the at least one holefrom analysis of the image comprises calculating a location of the atleast one hole in a coordinate system of an image recording system.Optionally, recording a pattern comprises photosensitizing said upperlayer and scanning a pattern onto the upper layer with a laser directimaging system. Optionally, recording a pattern comprisesphotosensitizing said upper layer and imaging a pattern onto the upperlayer through a mask. Optionally, the at least one hole a plurality ofholes arranged in a non-periodic hole pattern. Optionally, holes formingthe hole pattern do not pass through at least a layer of saidmulti-layered printed circuit board substrate. Optionally, holes formingthe hole pattern pass through each layer of said multi-layered printedcircuit board substrate.

[0039] There is further provided, in accordance with an embodiment ofthe invention, a method of image alignment, comprising:

[0040] producing an array of elements arranged in a non-periodic patternon said image; and

[0041] matching said pattern with an identical pattern, such that saidimage is aligned when the patterns overlay each other,

[0042] wherein fewer than 50% of the elements of the alignment patternin the image overlay the pattern in the identical pattern for anyposition in which the patterns are not aligned.

[0043] There is further provided, in accordance with an embodiment ofthe invention, apparatus for recording an electrical circuit pattern onan upper layer of a multi-layer printed circuit board substrate,comprising:

[0044] an alignment pattern generator generating an alignment patternthat is visible on the upper surface of the multi-layer printed circuitboard substrate, said alignment pattern having a known orientation withrespect to an electrical circuit pattern formed on one non-upper layerof the substrate, said substrate having at least two layers of circuitryalready formed thereon;

[0045] an alignment pattern location sensor sensing a location of thealignment pattern; and

[0046] an electrical circuit pattern generator recording an electricalcircuit pattern on said upper surface in a desired orientation withreference to the alignment pattern.

[0047] Optionally, the alignment pattern generator is a micro machiningdevice, optionally, a laser drill.

[0048] In an embodiment of the invention, the alignment pattern isdefined by a plurality of holes in said upper surface. Optionally,plurality of holes is arranged in a non-periodic pattern.

[0049] Optionally, where the alignment pattern is defined by a pluralityof micro-machined holes, the micro-machined holes do not pass through atleast one layer in said multi-layered substrate. Optionally, theplurality of micro-machined holes is arranged in a non-periodic pattern.

[0050] In an embodiment of the invention, the alignment pattern isdefined by a plurality of objects deposited on said upper surface, theobjects being arranged in a non-periodic pattern. Optionally, theplurality of objects is a plurality of markings. Optionally, themarkings are dimples.

[0051] In an embodiment of the invention, the alignment pattern locationsensor comprises a digital camera and an image processing circuitoperative to acquire an image and compute a location of said alignmentpattern. Optionally, the location of the alignment pattern is computedin a coordinate system employed by said electrical circuit patterngenerator. Optionally, the upper layer includes a photosensitizedsurface and the electrical circuit pattern generator is a laser directimaging scanner selectively recording an electrical circuit pattern onthe photosensitized surface. Optionally, the upper layer includes aphotosensitized surface and the electrical circuit pattern generatorcomprises a phototool mask and a light projector projecting lightthrough the phototool mask onto the photosensitized surface toselectively record an electrical circuit pattern thereon.

[0052] There is further provided, in accordance with an embodiment ofthe invention, apparatus for aligning a first electrical circuit patternto be recorded on an upper layer of a multi-layer printed circuit boardsubstrate to a second electrical circuit pattern formed on a lower layerof the multi-layer printed circuit board substrate, comprising:

[0053] an alignment pattern location sensor sensing a location of analignment pattern located on a multi-layered printed circuit boardsubstrate, said alignment pattern having a known orientation to saidsecond electrical circuit pattern; and

[0054] an electrical circuit pattern generator recording an electricalcircuit pattern on said upper surface in a desired orientation withreference to the alignment pattern.

[0055] Exemplary embodiments of the invention is described in thefollowing sections with reference to the drawings. The figures aregenerally not to scale and the same or similar reference numbers areused for the same or related features on different drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0056]FIG. 1 shows a perspective drawing of a scanner, in accordancewith the prior art;

[0057]FIG. 2 shows a perspective drawing of a portion of the scanner ofFIG. 1, related to the determination of printed circuit board positionin accordance with the prior art;

[0058]FIG. 3 shows a perspective drawing of a scanner in accordance withan embodiment of the invention;

[0059]FIG. 4 shows a perspective drawing of a portion of the scanner ofFIG. 3, related to the determination of printed circuit board positionin accordance with an embodiment of the invention;

[0060]FIG. 5A is a simplified flow diagram of a method of determining animager-scanner transform in accordance with an embodiment of theinvention;

[0061]FIG. 5B is a simplified flow diagram of a method of calculatingoffset corrections between imagers and scanner prior to imaging acircuit pattern;

[0062]FIG. 5C is a simplified flow diagram of an alternative method ofdetermining an imager-scanner transform in accordance with an embodimentof the invention;

[0063]FIG. 6 shows a perspective drawing of an array of calibrationand/or alignment patterns written on a substrate;

[0064]FIG. 7 is a simplified diagram showing calibration transformationsbetween imager coordinate space and scanner coordinate space; and

[0065]FIG. 8 is a simplified flow diagram of a method of computingposition corrections in the field of view of an imager, such as acamera, used in scanner, in accordance with an embodiment of theinvention.

[0066]FIG. 9A shows a perspective drawing of a multi-layer printedcircuit board having optical openings for viewing an alignment patternon a lower layer thereof;

[0067]FIG. 9B shows a simplified pictorial illustration of a methodologyfor manufacturing sequential build up printed circuit boards inaccordance with an embodiment of the invention;

[0068]FIG. 9C is a simplified flow diagram of a method of aligning theimage to be written on an upper layer with an image already formed onthe lower layer for the circuit board of FIG. 9A;

[0069]FIG. 10A is shows a perspective drawing of a portion of amulti-layer printed circuit board having vias and, optionally, alignmentholes, formed between the upper and lower layers;

[0070]FIG. 10B shows a simplified pictorial illustration of amethodology for manufacturing sequential build up printed circuit boardsin accordance with another embodiment of the invention;

[0071]FIG. 10C is a simplified flow diagram of a method of aligning theimage to be written on an upper layer with an image already formed onthe lower layer for the circuit board of FIG. 10A; and

[0072]FIG. 11 is an alternative calibration and/or alignment pattern, inaccordance with an embodiment of the invention.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

[0073]FIGS. 3 and 4 show an embodiment 200 of the present invention,which includes apparatus enabling the use of a new method of determiningthe relative position of the printed circuit board in the scanner usefulfor aligning images to be written on the respective opposing sides of aprinted circuit board.

[0074] In this system, a principal difference from the prior art systemof FIGS. 1 and 2 resides in the mechanism for determining a referencefor the scanner for writing an electrical circuit pattern.

[0075] Scanner-Imager Coordinate Calibration

[0076] It is appreciated that in order to align patterns that aresequentially recorded on a substrate a mechanism is required tocoordinate between the respective location of the subsequently recordedpatterns. In exemplary embodiments of the invention, an acquired imageof a reference pattern is employed. It is desirable to tie together thelocation of the reference pattern in images to coordinate space of thescanner system to ensure that recorded patterns are properly alignedwith respect to the reference pattern.

[0077] As shown in FIG. 3, system 200 includes two downward facingimagers 202, such as CCD cameras, mounted on a base 204. In theexemplary embodiment shown, bases 204 are moveably mounted on a rail206. Movement of the imagers 202 along the rail may be manual or may bemotorized using a motor (not shown) attached to the bases 204 or byother means as known in the art. Alternatively or additionally, the railis formed with detents 207, into which matching elements, such as, forexample, spring loaded elements, fit to selectively position the base atany one of a number of fixed positions. Additionally or alternatively,an encoder 208 may be used to determine the position of the base (andthus the imager) along the rail. Encoder 208 may be an optical encoderthat determines the position based on a reading of markings 210 on rail206. Alternatively, encoder 208 may be a mechanical encoder thatmeasures the movement of the base along the rail. Any other type ofsuitable encoder or other suitable positioning method or method ofmeasuring position, as known in the art, may be used. Alternatively, theimagers are fixed in place. Alternatively, as described below, a singlecamera may be used. Alternatively, more than two imagers may be used.Alternatively, cameras 202 may be fixed in place and folding mirrors(not shown) may be moveable along rail 206. It is noted that for thevarious imager configurations, arrangements may need to be provided toenable suitable movement of imagers 202 for adjustment of focusing.

[0078] Imagers 202 are positioned such that they view one or morefeatures 151, which may be generated by the scanner or other suitablefeature generation device. The image(s) of the feature(s) is(are)analyzed by an image analyzer 209 (which may be a properly programmedcomputer or other device known in the art) to determine the position ofthe feature in the coordinate system defined by the field of view of theimagers. These positions are fed to a computational system 212, whichmay be a general or special purpose computer or other circuitry. Thecomputational system is referred to herein, for simplicity, as “computer212”. Computer 212 also receives an indication of the relative positionof the imagers on the rail (when the imagers are not fixed). Thisindication may be sent to the computer by encoders 208, or, especiallywhere manual movement and detents are used to position the imager, maybe inputted manually to the computer.

[0079] Computer 212 also generally includes information regarding therelationship between the imager coordinate system and the scannercoordinate system (shown in FIG. 4 as being in an image-scannertransform memory 211), such that the measured position of the featuresin the imager coordinate system can be translated into the scannercoordinate system. In general, it is desirable (but may not be essentialin all cases) to determine a transformation between the coordinatesystems.

[0080] Reference is made to FIG. 7 which is a diagram illustratingcalibration transformations that are performed in exemplary embodimentsof the invention. Calibration between the imager coordinate system andthe scanner coordinate system should account for mutual X, Y translationof a point 720 in imager coordinate space and scanner coordinate spacerespectively, angular alignment an of imager coordinate space relativeto scanner coordinate space, and the size of a pixel in imagercoordinate space compared to the size of a pixel written by the scanner.

[0081]FIG. 5A is a flow diagram of an exemplary method 500 ofdetermining the translation of the coordinate systems in a calibrationstage typically performed prior to scanning a batch of printed circuitboard substrates to record an image of an electrical circuit patternthereon.

[0082] First (502) a bare photosensitized substrate 78 is placed on thescanner. For the purposes of calibration, no particular orientation ofthe substrate is necessary, provided that a pattern, or patterns, may bewritten on the substrate, and that substrate 78 is held in a fixedorientation to a stage 79 (FIG. 3) during the writing and the subsequentimaging by imagers 202.

[0083] Next, a “target” pattern 151 of a known size, orientation andposition in is written (504) on the sensitized substrate by scannersystem 200. In one embodiment of the invention, the sensitized materialis of a type that produces a visible “latent” or “printout” image whichcan be seen even without development or etching when exposed to the(generally, but not always, UV) light used to write the pattern on thesensitized substrate. A suitable substrate for use in the calibrationprocess which forms a visible “latent” image when exposed to UV light ofa scanner system is Dulux Registration Master photosensitive sheetsavailable from DuPont.

[0084] In exemplary embodiments of the invention, the target pattern orpatterns for calibration are written onto the photosensitive substratesuch that they can be viewed from one or more positions at which theimager can be placed, and in particular, at positions at or near wherethe imagers are placed to view alignment patterns written on thesubstrate during scanning. The pattern is written on a portion of thesubstrate that is located under the scanning line 213 shown in FIG. 4.Optionally an array of alignment patterns is written and the patterns inthe array are viewed sequentially.

[0085] A plurality of alignment patterns 151 is optionally written atvarious imager positions such that these patterns can be imaged by oneor more imagers 202 (FIG. 3 and FIG. 4).

[0086] Then the scanner 200 moves the substrate (506) such that thepatterns are in a position for viewing by the imager(s). The imagers areplaced in position (when they have to be used) so that they sequentiallyview each of the patterns 151, and the location of each pattern 151 isstored in image-scanner transform memory 211. As is well known and as isshown in FIGS. 1 and 2, scanners are provided with very accurate meansfor measuring the movement of the substrate in the cross-scan direction,as well as for determining the precise location at which a beam 16records data in the scan direction.

[0087] The imagers acquire images of the patterns (508) and pass them toanalyzer 209, which may be, in a practical situation hardware andsoftware associated with computer 212.

[0088] Analyzer 209 computes a reference location of each pattern, forexample a center point, a corner point, or some other reference point inthe pattern, with respect to the particular imager coordinates andpasses the information to computer 212.

[0089] Computer 212 calculates (510) the position, orientation andscaling of the patterns in the imager coordinate system. Thiscalculation may be determined, for example, by determining the positionof the pattern in the imager coordinate system and then transformingthis position by the measured movement of the substrate. Suitablemethods for determining the location of the pattern in the imagercoordinate system include blob analysis and pattern matching. It may behelpful to calibrate the imagers against each other by having them viewthe same pattern, without moving the pattern. To do this, the imagersare sequentially positioned to view the pattern (for example using thesame detent for more than one imager). The positions (and optionally theorientations) of the images is used to determine a transformation whichcorrects for the differing placements of the imagers on their respectivebases.

[0090] Computer 212 also receives information as to the distance movedby the substrate during the movement (512), as described above.

[0091] Computer 212 computes a transform (514) between the coordinatesystems of each imager and of the scanner respectively. This transformis based on the known positions at which a calibration pattern waswritten in the scanner coordinate system, the distance the boardtraveled and the position of the pattern in the imager coordinatesystem. This transformation may be stored in memory locations incomputer 212, which may be a general purpose computer or a specialpurpose computer.

[0092] This transform (including information relating the coordinatesystems of the various imagers in the various positions to the overallimager coordinate system) is stored, for example in image scannertransform memory 211, for use by the computer.

[0093] The patterns 151 may be a simple cross-hair pattern or they maybe a more complex pattern. Alternatively, the pattern may comprise aseries of crosses or dots.

[0094] Reference is now made to FIG. 6 which illustrates an array 251 ofexemplary patterns 151 employed to calibrate X, Y translation betweenthe imager coordinate space and scanner coordinate space. As seen inFIG. 6, array 251 comprises a plurality two dimensional patterns 151generally extending the length of an edge of substrate 78, wherein eachpattern 151 is formed of a 3×3 matrix of equidistant dots. As seen inthe exemplary pattern appearing in FIG. 6 a suitable pattern comprises a2-dimensional 3×3 array of 0.08″ diameter dots mutually spaced apart by0.1″. Other suitable arrays of patterns, including suitably sized dotsand distances between the dots, may also be used.

[0095] These patterns, when written by a scanner system, allow for thedetermination of X and Y translation distances, precise determination ofa center point of the pattern for calibration of a transform, and anangular orientation of an imager in space relative to the scanner so asto enable compensation for angular offset, distortion, and differencesin magnification between extremities of an image acquired by the imager,and coordination of camera pixel size to scanner pixel size.

[0096] It is noted that when an array 251 of patterns 151 is used, theposition for each pattern is determined and its respective translationis stored in a data base thus correlating position translation of imagerfor a series of locations. Moreover, the calculation may be based onmovement of the substrate, location of an imager 202 with respect toeach pattern 151 in array 251 and the location of the reference point ineach of images 151 in the field of view of an imager 202.

[0097] The calibration described with respect to FIG. 5A may be repeatedas desired to assure that there is no change in the transformation. Itcould even be performed on each PCB, although this is seldom necessary.However, since the method requires writing of a particular calibrationpattern each time, it is also possible to perform a simplified check onthe transformation, as described with reference to FIG. 5B, which showsa method 530 which may result in a correction to the basic alignmentachieved by the method of FIG. 5A. In accordance with some embodimentsof the invention a jig 161, comprising a through hole 163, attached tobase 79 is provided to facilitate coordinate space alignment between thecoordinate systems of imagers 202 and scanner system 200.

[0098] As seen in the flow chart of FIG. 5B, image scanner coordinatetransform data, for example, as derived using the method of FIG. 5A, isreceived (516). The location of hole 163 is determined using an imager(518) and transformed to scanner coordinates using the transform. Thelocation of hole 163 is also determined in the coordinate system ofscanner 200 using beam 16 (520). A suitable method for determining thelocation of hole 163 using beam 163 is described in PCT patentpublication WO 00/02424 and with respect to FIG. 2 above. Beam 16 isscanned over hole 163, and a collector 152 is provided underneath base79 to, collect light inputs as beam scans the hole. On-off modulation,as the beam passes the hole, of the signal from the light collectorenables precise determination of the location of edges of hole 163, andprecise determination of the location of the center of hole 163therefrom. The location of hole 163 as determined by an imager 202 andcorrected by the imager scanner coordinate transform, and the holelocation determined using beam 16 are compared (522) and aligned toensure precise correlation between imager coordinate space and scannercoordinate space for each scan. The alignment factor is stored incomputer 212.

[0099]FIG. 5C shows another method (580) for determining a transformbetween the imager and scanner coordinate systems respectively. In thismethod a series of patterns of holes, such as holes in the pattern shownin FIG. 6 is formed in a calibration board (582). Alternatively, simplerpatterns may be formed.

[0100] The coordinates of the pattern are determined in scanner spaceusing the method described in PCT patent publication WO 00/02424 andwith respect to FIGS. 2 and 5B above (584). The board is then moved(586), together with the table, the accurate table-motion measuringsystem built in to the scanner.

[0101] The imagers acquire images of the patterns (588) and pass them toanalyzer 209, which may be, in a practical situation hardware and/orsoftware associated with computer 212.

[0102] Analyzer 209 computes (590) a reference location of each pattern,for example a center point, a corner point, or some other referencepoint in the pattern, with respect to the particular imager coordinatesand passes the information to computer 212.

[0103] Computer 212 calculates (590) the position, orientation andscaling of the patterns in the imager coordinate system. Thiscalculation may be determined, for example, by determining the positionof the pattern in the imager system and then transforming this positionby the measured movement of the substrate. It may be helpful tocalibrate the imagers against each other by having them view the samepattern, without moving the pattern. To do this, the imagers aresequentially positioned to view the pattern (for example using the samedetent for more than one imager). The positions (and optionally theorientations) of the images is used to determine a transformation whichcorrects for the differing placements of the imagers on their respectivebases.

[0104] While this system does allow for the determination of an accuratetransform, it requires the production of a special printed circuit boardjig and the provision of a table with holes and a detector such asdetector 152, 153 shown in FIG. 2.

[0105] Computer 212 also receives information as to the distance movedby the substrate during the movement (592), as described above.

[0106] Computer 212 computes a transform (594) between the coordinatesystems of each imager and of the scanner respectively. This transformis based on the known positions at which a calibration pattern waswritten in the scanner coordinate system, the distance the boardtraveled and the position of the pattern in the imager coordinatesystem. This transformation may be stored in memory locations incomputer 212, which may be a general purpose computer or a specialpurpose computer.

[0107] This transform (including information relating the coordinatesystems of the various imagers in the various positions to the overallimager coordinate system) is stored, for example in image scannertransform memory 211, for use by the computer.

[0108] In some embodiments of the invention greater accuracy indetermining the transform and greater accuracy in determining theposition of alignment patterns can be achieved by calibrating the fieldof view of the imager itself. A method 600 of performing suchcalibration is shown schematically in the flow chart of FIG. 8. In someembodiments of the invention, calibration of the field of view of theimager is performed as a single step along with determination of thetranslation of the coordinate systems.

[0109] A calibration pattern is provided (602) for viewing by theimager. In an embodiment of the invention, an accurate pattern, forexample an array of precisely sized and positioned dots appearing as apattern 151 in FIG. 6, is scanned onto or formed in a substrate byscanner system 200. In some exemplary embodiments, it is sufficient touse a single pattern 151 for the purpose of field of calibration,although improved results may be obtained by using multiple patterns151.

[0110] The patterns and imagers are moved to enable viewing of thepatterns by respective imagers and images of the calibration patterns isacquired (604). The locations of the pattern elements forming patterns151 in the coordinate system of the imager are determined (606) by imageanalyzer 209 or by computer 212 and compared (608) to the actualrelative positions of the elements on the pattern, determined, forexample from knowledge of the location where they are recorded byscanner system 200.

[0111] Due to variations in the magnification of the image pattern asseen by the imager, distortion, angular orientation of the imager inspace not in alignment with respect to the scanner, and aberrations inthe imager optics, the position and size of the elements on the image(in the coordinates of the particular imager) may not preciselycorrespond to those of the actual pattern. Analysis of the image enablesphysical adjustment of the imager to partially align the imager relativeto the scanner. Additionally, computer 212 computes a calibrationtransformation (610) to transform imager coordinate position with theactual position in the field of view of the imager to calibrate pixelsize of pixels in the imager to the pixel size of pixels written by thescanner and to correct for any remaining, magnification errors,distortions or other image aberrations.

[0112] It should be understood that the actual position of the patternis not critical since it is the relative positions, spacings and/or sizeof the elements of pattern in the field of view of the imager that isused to calibrate the field of view of an imager. This transformation isused in all measurements made with the imager, as for example, themeasurements of position of a pattern as in the method of FIG. 5 or inthe position of an alignment pattern in a substrate. The corrections forpixel size may be a single value as a function globally correcting forall pixels, or a function taking into account magnification errors,distortions and aberrations that are not uniform over the entire fieldof view of an imager 202.

[0113] It should be understood that the methods of FIGS. 5 and 8 can beperformed in essentially a single operation by writing a pattern on asensitized substrate that can be used for both determining a coordinatetransformation between the imager and scanner systems and an internalcalibration of the field of view of the imagers. For example, if apattern comprising an array of equally spaced elements (such as dots orcross-hairs having different extent from the central one) is written onthe board, a center point of the array can be calculated and used todetermine the coordinate transform between the imager system and thescanner system. Alternatively, a cross hairs indicating a particularreference point along with additional elements may be provided. Eitherway, the plurality of elements can be used to calibrate the field ofview of the imager itself and calibrate the coordinate space of thefield of view of the imager to correspond to the coordinate spaced ofthe scanner.

[0114] The transform may be stored in image analyzer 209 and may be usedto correct images received from imagers 202 before any processing isperformed on or using them.

[0115] Sequential Build up Alignment

[0116] Reference is made to FIG. 9A which shows a printed circuit board900 formed of a lower layer 902 and an upper layer 904 in accordancewith an exemplary embodiment of the invention, to FIG. 9B which shows asystem for recording an image on an upper layer 904 with reference to aregistration target on a lower layer 902 in accordance with an exemplaryembodiment of the invention, and to FIG. 9C which shows a flow chart foraligning coordinate system of an exposure system with the patternwritten on lower layer 902 in accordance with an exemplary embodiment ofthe invention.

[0117] In FIG. 9A, a portion of upper layer 904 is cut away to enablevisualization of a pattern 906 formed on lower layer 902. It isappreciated that lower layer may be a single layer as shown in FIG. 9A,or a core of a printed circuit board formed of several layers as shownin FIG. 9B. Pattern 906 forms part of an electrical circuit 908 and oneor more alignment markings 910. Alignment markings 910 may comprise asingle dot, a rectangular array of dots, such as the 3×3 array 151 (FIG.9A), a cross or series of crosses, a pair of vertex-to-vertex triangles951 (FIG. 9B), an array of dots 1151 arranged in a non-periodic patternsuch as that shown in FIG. 1A, or any other suitable pattern.

[0118] In the exemplary embodiment shown in FIG. 9A, upper layer 904 isformed with one or more windows 914 through which alignment markingslocated on lower layer 902 can be seen, even when the upper layer 904 isin place. It is appreciated that the alignment markings may be locatedon the lower layer that is immediately below upper layer 904, or on anylower layer located within in a core of several layers. The windows 914may be actual physical openings formed in upper layer 904.Alternatively, if the upper layer is formed of a dielectric and aphotoresist that are at least partly transparent, it is sufficient toomit the copper cladding on the upper layers in the alignment regions.

[0119] A dot pattern 1151, shown in FIG. 11, may be useful as analignment pattern 151 (FIG. 9A) for alignment of layers. The array shownin FIG. 11 is particularly useful in automatic alignment systems and insystems in which the quality of the image may be poor, since thecorrelation for offsets that are one or two rows or columns is muchlower than that for proper alignment. Thus, the pattern shown provides awide tolerance for unprinted dots or the like. It is noted that pattern1151 may be defined either by holes, for example by laser drillingthrough some or all of the layers defining a printed circuit boardsubstrate, or by a pattern written by a scanner or otherwise formed in aprinted circuit board.

[0120] As seen in FIG. 11, pattern 1151 is formed of an array ofsuitably sized dots 1152 which are spaced apart in a generallynon-periodic arrangement. The dots may be defined by drilled holes (forexample drilled by laser or mechanical means), printed patterns,impressions or any other suitable markings. As appreciated from FIG. 11,due to the non-periodic arrangement of pattern 1151, if two identicalpatterns are superimposed one on top of the other but are partiallyoffset from each other along either the X axis or along the Y axis, orotherwise, even if at least one row or column is mutually aligned amongthe patterns, then only a small number of dots of the two patterns willoverlay each other. This is in contrast to regular matrices of patternsin which, even when the patterns are offset, most of the dots willoverlay each other. In a 2×2 regular matrix of elements, 50% of the dotsin one matrix will be aligned with dots in the other matrix, even whenthe pattern is not in alignment and in a 3×3 regular matrix up to ⅔ ofthe dots can be aligned without the pattern being fully aligned.

[0121] In contrast, in accordance with embodiments of the presentinvention, the overlap of dots is always less 50% and optionally lessthan 40, 30, 20 or 15%. In the exemplary embodiment according to FIG. 11having 29 dots, no more than four dots can overlap for any non-alignedposition (less than 14%). It will be clear, to a person of skill in theart that larger or smaller non-periodic arrays can be generated thathave a larger or smaller percentage of maximum dots aligned in anon-aligned condition.

[0122] In accordance with an exemplary embodiment of the invention, seenin FIG. 9B, a micro-machining device, such as a driller 920, is providedat a first workstation to produce micro-via holes 922 in a substrate 900formed of an upper layer 904 and several lower layers 902. Substrate 900may be provided with through holes 924 which may be drilled either bydriller 920 or other suitable drilling apparatus.

[0123] It is appreciated that upper layer 904 seen in FIG. 9B is cutaway to expose part of a pattern 906 on the uppermost part of lowerlayers 902. Typically, driller 920 includes a sensor unit 926, such as adigital camera, or other suitable sensor, and suitable image processingcircuitry (not shown) operative to image one or more suitable alignmenttargets, such as an unveiled target 951, and determine their respectivelocations. Microvia holes 922 and through holes 924 are formed atlocations aligned with referenced to the location of target 951.

[0124] In a separate step, typically performed at a work stationseparate from driller 920, a pattern recording system 930 is provided torecord electrical circuit patterns 932 on upper surface 904. Inexemplary embodiments of the invention, pattern recording system is alaser direct imaging system such as a DP-100 laser direct imaging systemavailable from Orbotech Ltd. of Yavne, Israel, configured with imagerssubstantially as described hereinabove with reference to FIGS. 3 & 4. Inexemplary embodiments of the invention, pattern recording system 930 isoperative to dynamically scale pattern data in response to therespective locations of several alignment fiducials 951, as described inPCT patent publication WO 00/02424. It is appreciated that othersuitable pattern recording systems, such as conventional steppers andprojectors exposing a photosensitive coating through suitable phototoolscontaining an image of a pattern to be recorded, may be employed torecord patterns 932 on substrate 900.

[0125] As seen in FIG. 9B, system 930 includes an imager 934 whichimages alignment targets 951 and provides location information relatingto alignment targets to a data controller 936, typically followingsuitable analysis and computation in computational means as described ingreater detail with respect to FIG. 4. Data controller suitably adjuststhe location of pattern 932 on upper surface 904 in response to thelocation of target 951.

[0126]FIG. 9C shows a flow chart (960) for aligning the scannercoordinate system with the pattern written on the lower layer 902,useful in recording of an image of an electrical circuit pattern asshown in FIG. 9B.

[0127] Prior to scanning a batch of electrical circuits, the coordinatespace of the imager 202 and of the pattern recording system 930, such asscanner system 200 (FIG. 3), are calibrated and aligned (961) forexample, as described above and with reference to FIGS. 1-8.

[0128] A substrate on which an electrical circuit pattern is to bewritten on an upper layer 904 thereof is placed on the scanner (962).The substrate is formed so that its outer surface is coated with aphotoresist and at least a portion of the surface is non-opaque. Thenon-opaque portion may be a portion that is formed, for example, by notapplying copper to a translucent substrate, or that is formed by cuttingin the substrate. In accordance with some embodiments of the invention,the non-opaque portion overlays an alignment pattern formed on the lowerlayer, as shown in FIGS. 9A and 9B.

[0129] Images of unveiled alignment patterns (951 in FIG. 9B) visiblethrough the non-opaque portions of the substrate are acquired (964), andthe position of the alignment patterns in imager coordinate space iscalculated (966). In exemplary embodiments of the invention, usingtransform data stored in image-scanner transform obtained from apreviously performed calibration, for example as described hereinabovewith respect to FIGS. 5 and 8 the position of the alignment pattern istransformed to a position in scanner coordinate space (968).

[0130] Once the position of the alignment patterns is known in scannercoordinate space, the substrate may be optionally rotated by thescanner, based on the measurements, as necessary to obtain rotationalalignment to the grid pattern of the scanner system. See elements 157,158 and 160 in FIG. 4. A circuit pattern is written with reference tothe position of the alignment patterns in scanner coordinate space(970). It is noted that multiple alignment patterns may be provided andthe pattern written is scaled with reference to the mutual locations ofthe patterns. The substrate subsequently is removed from the scanner,the exposed circuit pattern written by the scanner is developed (972)and etched (974) to form part of an electrical circuit.

[0131] It is appreciated that although FIG. 9B shows vias being formedprior to imaging by system 930, vias between the layers may be formedeither before or after recordation of the circuit on the upper layer.

[0132] Reference is made to FIG. 10A which shows a printed circuit boardsubstrate 1000 formed of a lower layer 1002 and an upper layer 1004 inaccordance with an exemplary embodiment of the invention, to FIG. 10Bwhich shows a system for recording an image on a upper layer 1004 withreference to a registration target formed on upper layer in accordancewith an exemplary embodiment of the invention, and to FIG. 9C whichshows a flow chart for aligning coordinate system of an exposure systemwith the pattern written on upper layer 1002 in accordance with anexemplary embodiment of the invention.

[0133] In FIG. 10A, a portion of the upper layer 1004 is cut away toenable visualization of a pattern 1006 formed on lower layer 1002. It isappreciated that lower layer may be a single layer as shown in FIG. 10A,or a core of a printed circuit board formed of several layers as shownin FIG. 10B. Pattern 1006 forms part of an electrical circuit 1008,which typically includes, inter alia, conductor parts, viasinterconnecting between electrical circuit parts on various layers inthe electrical circuits, landing pads formed on a lower layer to receivea via, and annular rings surrounding a via on an upper layer.

[0134] In the exemplary embodiment shown in FIG. 10A, upper layer 1004is formed with one or more vias which are aligned with a pattern 1008formed on lower layer 1002. These via may be of two types, namelyconnection vias 1010 which are necessary to connect between electricalcircuit elements 1008 formed on the lower layer 1002 and electricalcircuit elements (not shown) formed on upper layers 1004 respectively,and alignment pattern vias 1012 forming alignment patterns for alignmentof the pattern to be written on the upper layer 1004 with the pattern1006 already formed on the lower layer. Alignment pattern vias 1012forming an alignment pattern typically are dedicated for use as analignment pattern and are not otherwise used. Alternatively oradditionally, through alignment holes 1024 (FIG. 10B), passing throughall of the layers forming printed circuit board substrate 1000, may beprovided.

[0135] As is well known in the art, the placement of such alignment ofholes and vias may be determined, with reference to x-ray images of someor all of the bonded upper and lower layers, or with reference tounveiled alignment targets 1051 (FIG. 10B). The accuracy of placement ofvias and through holes is a function of the tolerance of machiningapparatus employed to form the vias an through holes. It is appreciatedthat in exemplary embodiments, the pattern of vias and holes is arrangedas described with reference to FIG. 11. Suitable laser drilling systemsoperative to drill vias with reference to a target are available fromElectro Scientific, Inc. of Oregon, U.S.A.

[0136] In accordance with an exemplary embodiment of the invention seenin FIG. 10B, a micro-machining device, such as a driller 1020, isprovided at a first workstation 1021 to drill micro-via holes 1022 in asubstrate 1000 formed of an upper layer 1004 and several lower layers1002. Substrate 1000 may be provided with through holes 1024, that aredrilled either by driller 1020 or other suitable machining apparatus. Atleast some of the holes formed by driller 1020 are alignment patternholes 1012 defining a via hole alignment pattern 1013 that is employedin the manufacture of a printed circuit board as described in greaterdetail hereinbelow. Alignment holes 1012 optionally may be formed oversuitable landing pads or copper base (not shown).

[0137] It is appreciated that upper layer 1004 is cut away to exposepart of a pattern 1006 on the uppermost part of lower layers 1002.Typically, driller 1020 includes a sensor unit 1026, such as a digitalcamera and suitable image processing circuitry (not shown) operative toimage and determine the location of one or more alignment targets, suchas an unveiled target 1051. The respective locations of micro-via holes1022 and through holes 1024 are formed at locations aligned withreference to the location of target 1051.

[0138] In a separate step, typically performed at a work stationseparate from driller 1020, a pattern recording system 1030 is providedto record electrical circuit patterns 1032 on upper surface 1004. Inexemplary embodiments of the invention, pattern recording system is alaser direct imaging system such as a DP-100 laser direct imaging systemavailable from Orbotech Ltd. of Yavne, Israel, configured with at leastone imager 1034 substantially as described hereinabove with reference toFIGS. 3 & 4.

[0139] It is a feature of some exemplary embodiments of the presentinvention that in system 1030 pattern 1032 is recorded on upper surface1004 in alignment referenced to via hole alignment pattern 1013, which,being formed by driller 1020, is in precise alignment with other viaholes 1022. In some exemplary embodiments, an upper layer alignmenttarget 1052 is recorded on upper surface 1004 to serve as an alignmenttarget for aligning micro-vias in subsequent sequential build up layersof substrate 1000.

[0140] As seen in FIG. 10B, system 1030 includes a sensor 1034 whichimages alignment via hole alignment pattern 1013 and provides locationinformation to a data controller 1036, typically following suitableanalysis and computation in computational means as described in greaterdetail with respect to FIG. 4, which suitably adjusts the location ofpattern 1032 on upper surface 1004.

[0141] In some exemplary embodiments of the invention, pattern recordingsystem 1030 is operative to dynamically scale pattern data in responseto the respective locations of several via hole alignment patterns 1013,as described in PCT patent publication WO 00/02424. It is appreciatedthat other suitable pattern recording systems, such as conventionalsteppers and projectors exposing a photosensitive coating throughsuitable phototools containing an image of a pattern to be recorded, maybe employed to record patterns 1032 on substrate 1000 with reference tovia hole alignment patterns 1013.

[0142] It is noted use of via hole alignment patterns 1013 to alignpattern 1032 facilitates the positioning of annular rings concentricallywith via holes 1022. Thus although printed circuit board produced usinga sequential build-up methodology described with reference to FIG. 10Bmay exhibit an overall drift, annular rings 1040 in each sequentiallayer are precisely aligned with micro-vias formed in upper layer 1004,typically to within tolerances that are less than the tolerances whichare possible if alignment is referenced to the same target employed toposition via holes 1022.

[0143] Moreover, it is noted that the tolerances required of annularrings 1042 surrounding through holes typically are larger than thetolerances required of annular rings 1040 surrounding micro-vias 1022.Thus in some exemplary embodiments of the invention, pattern 1032 isaligned to via a hole alignment pattern 1013 (and thus to vias 1022).This typically results in annular rings 1040 being closely concentricwith vias 1022, while annular rings 1042 are slightly off center withrespect to through holes 1042.

[0144]FIG. 10C shows a flow chart (1060) for aligning the scannercoordinate system with the pattern written on the lower layer.

[0145] Prior to scanning a batch of electrical circuits, the coordinatespace of the imager 202 and of the scanner system are calibrated forexample, as described above and with reference to FIGS. 1-8.

[0146] A substrate on which an electrical circuit pattern is to bewritten on an upper layer is placed on the scanner (1062). The substrateis formed so that its surface is coated with a photoresist.

[0147] Prior to scanning an electrical circuit pattern onto thesubstrate, imager coordinate space and scanner coordinate space arealigned (1061) as described hereinabove.

[0148] Images of alignment patterns (one or more of the usable vias, thealignment vias or the alignment holes) are acquired (1064), and theposition of the alignment patterns in imager coordinate space iscalculated (1066). In exemplary embodiments of the invention, usingtransform data stored in image-scanner transform obtained from apreviously performed calibration, for example as described hereinabovewith respect to FIGS. 5 and 8, the position of the alignment pattern istransformed to a position in scanner coordinate space (1068).

[0149] Once the position of the alignment patterns is known in scannercoordinate space, the substrate may be optionally rotated by thescanner, based on the measurements, as necessary to obtain rotationalalignment to the grid pattern of the scanner system. See elements 157,158 and 160 in FIG. 4. A circuit pattern is written with reference tothe position of the alignment patterns in scanner coordinate space(1070). It is noted that multiple alignment patterns may be provided andthe pattern written may be scaled with reference to the mutual locationsof the patterns. The substrate subsequently is removed from the scanner,the exposed circuit pattern written by the scanner is developed (1072)and etched (1074) to form part of an electrical circuit.

[0150] In available hole drilling devices, vias are drilled to provide abest fit to the lower board. However, the holes are drilled in a fixedpattern that does not take into account warping of the pattern writtenon the lower board as a result, for example, of variable shrinkage ofthe board during development and etching.

[0151] In some embodiments of the present invention, the hole patternsare drilled in positions determined by local features of the lowerlayer. These features may include alignment patterns especially writtenonto the lower board. Such patterns may be used to provide an overallshrinkage factor to be applied to the board or to provide a full warpingtransform to the board. In writing upper board, the data is adjustedeither on-the fly or by producing transformed data to fit the image tobe written onto the lower image.

[0152] Similarly, when the lower layer has a number of alignmentpatterns that are visible when the upper layer is in place, theplurality of patterns can be used to provide either an overall shrinkagecorrection (which may be different in the x and y directions) or a fullwarp correction.

[0153] Warp correction of data is well known in the art. The specificmethodology of providing such correction in a particular scanner is verydependent on the scanner itself. Thus, such particular methods are notdiscussed herein. However, application of the methods of the inventionis well within the skill of a person of skill in the art.

[0154] In some embodiments of the invention the various alignmentpatterns are offset predetermined distances from edges of the board inorder to facilitate determination of which side of the board is facingup, and whether a particular end of the board is its front end or backend. Thus for example, on side A of a board, alignment patterns may beprovided along lines that are located 0.5″ from the front end of theboard and 0.75″ from the back end of the board respectively, and alonglines that are 0.5″ from the right hand side and 0.75″ from the lefthand side. On side B of the same board, alignment patterns may beprovided along lines that are located 0.35″ from the front end of theboard and 0.6″ from the back end of the board respectively, and alonglines that are 0.35″ from the right hand side and 0.6″ from the lefthand side. It is appreciated that these values are merely representativeand that other suitable unique and differentiable values may be used todistinguish sides and edges. In this manner, it becomes a simplecalculation based on distance from an edge to determine whether a givenedge is on the front or back side, and whether it is a front, back, leftor right edge.

[0155] The invention has been described utilizing exemplary apparatusand exemplary methods. It should be understood that other apparatus maybe used in carrying out the methods and the methods described may beuseful in apparatus that is different from that described. For example,conventional projection exposure systems may be used to record patterns.Furthermore, since each of the methods is, in great measure, a standalone method, other methods may be utilized in determining one or moreof the calibrations described. In particular, it may be possible, undercertain circumstances, to delete or simplify one of the calibrations, asfor example when the devices are produced to a very high tolerance orwhere very high accuracy is not needed. In addition, while a systemusing two imagers has been described, a single imager may be used in oneof two ways. In a first embodiment, the imager has a large enough fieldof view to encompass multiple patterns on the substrate. Generally, thisembodiment will have a lower resolution and accuracy, but may be usefulfor some applications. A second method is to move the imager fromposition to position to image different patterns. Furthermore,variations in the methods described are also possible.

[0156] While the methods and apparatus described represent a “best mode’for carrying out the invention, it should be understood that someelements of the apparatus and claims may not be necessary for allembodiments of the invention and that elements of the variousembodiments may be combined.

[0157] As used herein, the terms “have”, “include” and “comprise” ortheir conjugates, as used herein mean “including but not necessarilylimited to”.

1. A method for aligning an image to be recorded by a direct imagescanner on an upper layer of a printed circuit board with an imagerecorded on a lower layer thereof, the method comprising: visuallyimaging a portion of the image on the lower layer; and recording apattern on the upper layer, referenced to coordinates of the visualimage of the portion.
 2. A method according to claim 1 wherein theportion is an alignment pattern recorded on the lower layer.
 3. A methodaccording to claim 2 and including forming an opening in the upper layerthrough which the alignment pattern is visible.
 4. A method according toclaim 2 wherein the alignment pattern is visible through the upperlayer.
 5. A method according to claim 1 wherein recording includes:providing an object aligned with the image portion; and recording thepattern on the upper layer, referenced to the object.
 6. A methodaccording to claim 5 wherein the object comprises holes formed in theupper layer.
 7. A method according to claim 5 and including: imaging theobject; and determining a position of the object, wherein the pattern isrecorded relative to the determined position.
 8. A method according toclaim 6 wherein the holes comprise holes that do not pass through thelower layer.
 9. A method according to claim 6 wherein the holes arevias.
 10. A method according to claim 9 wherein the holes comprisefunctional vias connecting patterns on the upper and lower layers.
 11. Amethod according to claim 6 wherein the images comprise electricalcircuits and wherein the holes are not related to an electrical functionof the printed circuit board.
 12. A method according to claim 6 whereinthe holes pass through the upper and lower layers.
 13. A methodaccording to claim 6 wherein the holes form an alignment pattern,referenced with the image on the lower layer.
 14. A method according toclaim 13 wherein the images comprise electrical circuits and wherein theholes are not related to an electrical function of the images
 15. Amethod according to claim 14 wherein the holes pass through the upperand lower layers.
 16. A method for aligning an image to be recorded by adirect image scanner on an upper layer of a printed circuit boardsubstrate with a pattern on a lower layer thereof, the methodcomprising: detecting at least one hole provided in the upper layer,said at least one hole being provided in predetermined alignment to saidpattern and said at least one hole not passing through said lower layer;and scanning a pattern on the upper layer in predetermined alignmentwith said at least one hole.
 17. A method for recording an image on anupper layer of a multi-layered printed circuit board substrate, themethod comprising: forming at least one hole in an upper layer of amulti-layered printed circuit board substrate, said at least one holehaving a known spatial orientation to a pattern formed on one layer ofthe substrate and said substrate having at least two layers of circuitryalready formed thereon; acquiring an image of the at least one hole;calculating a location of the at least one hole from analysis of theimage; and recording a pattern on the upper layer with reference to saidlocation.
 18. The method for recording an image according to claim 17and wherein forming at least one hole comprises forming at least onehole with a laser micro-machining device.
 19. The method for recordingan image according to claim 17 and wherein forming at least one holecomprises forming the at least one hole in at least the upper layer andnot forming at least one hole in at least another layer of saidmulti-layered printed circuit board substrate.
 20. The method forrecording an image according to claim 17 and wherein acquiring an imageincludes acquiring a digital image of the at least one hole.
 21. Themethod for recording an image according to claim 17 and whereincalculating a location of the at least one hole from analysis of theimage comprises calculating a location of the at least one hole in acoordinate system of an image recording system.
 22. The method forrecording an image according to claim 17 and wherein recording a patterncomprises photosensitizing said upper layer and scanning a pattern ontothe upper layer with a laser direct imaging system.
 23. The method forrecording an image according to claim 17 and wherein recording a patterncomprises photosensitizing said upper layer and imaging a pattern ontothe upper layer through a mask.
 24. A method according to claim 17wherein said at least one hole a plurality of holes arranged in anon-periodic hole pattern.
 25. A method according to claim 24 whereinholes forming said hole pattern do not pass through at least a layer ofsaid multi-layered printed circuit board substrate.
 26. A methodaccording to claim 24 wherein holes forming said hole pattern passthrough each layer of said multi-layered printed circuit boardsubstrate.
 27. A method of image alignment, comprising: producing anarray of elements arranged in a non-periodic pattern on said image; andmatching said pattern with an identical pattern, such that said image isaligned when the patterns overlay each other, wherein fewer than 50% ofthe elements of the alignment pattern in the image overlay the patternin the identical pattern for any position in which the patterns are notaligned.
 28. Apparatus for recording an electrical circuit pattern on anupper layer of a multi-layer printed circuit board substrate,comprising: an alignment pattern generator generating an alignmentpattern that is visible on the upper surface of the multi-layer printedcircuit board substrate, said alignment pattern having a knownorientation with respect to an electrical circuit pattern formed on onenon-upper layer of the substrate, said substrate having at least twolayers of circuitry already formed thereon; an alignment patternlocation sensor sensing a location of the alignment pattern; and anelectrical circuit pattern generator recording an electrical circuitpattern on said upper surface in a desired orientation with reference tothe alignment pattern.
 29. Apparatus for recording an electrical circuitpattern according to claim 28, and wherein said alignment patterngenerator is a micro machining device.
 30. Apparatus for recording anelectrical circuit pattern according to claim 29, and wherein micromachining device is a laser drill.
 31. Apparatus for recording anelectrical circuit pattern according to claim 28, and wherein saidalignment pattern is defined by a plurality of holes in said uppersurface.
 32. Apparatus for recording an electrical circuit patternaccording to claim 31, and wherein said plurality of holes is arrangedin a non-periodic pattern.
 33. Apparatus for recording an electricalcircuit pattern according to claim 29, and wherein said alignmentpattern is defined by a plurality of micro-machined holes, and whereinsaid micro-machined holes do not pass through at least one layer in saidmulti-layered substrate.
 34. Apparatus for recording an electricalcircuit pattern according to claim 33, and wherein said plurality ofmicro-machined holes is arranged in a non-periodic pattern. 35.Apparatus for recording an electrical circuit pattern according to claim28, and wherein said alignment pattern is defined by a plurality ofobjects deposited on said upper surface, said objects being arranged ina non-periodic pattern.
 36. Apparatus for recording an electricalcircuit pattern according to claim 35, and wherein said plurality ofobjects is a plurality of markings.
 37. Apparatus for recording anelectrical circuit pattern according to claim 36, and wherein saidmarkings are dimples.
 38. Apparatus for recording an electrical circuitpattern according to claim 28, and wherein said an alignment patternlocation sensor comprises a digital camera and an image processingcircuit operative to acquire an image and compute a location of saidalignment pattern.
 39. Apparatus for recording an electrical circuitpattern according to claim 38, and wherein said location of saidalignment pattern is computed in a coordinate system employed by saidelectrical circuit pattern generator.
 40. Apparatus for recording anelectrical circuit pattern according to claim 39, and wherein said upperlayer includes a photosensitized surface and said electrical circuitpattern generator is a laser direct imaging scanner selectivelyrecording an electrical circuit pattern on said photosensitized surface.41. Apparatus for recording an electrical circuit pattern according toclaim 39, and wherein said upper layer includes a photosensitizedsurface and said electrical circuit pattern generator comprises aphototool mask and a light projector projecting light through saidphototool mask onto said photosensitized surface to selectively recordan electrical circuit pattern thereon.
 42. Apparatus for aligning afirst electrical circuit pattern to be recorded on an upper layer of amulti-layer printed circuit board substrate to a second electricalcircuit pattern formed on a lower layer of the multi-layer printedcircuit board substrate, comprising: an alignment pattern locationsensor sensing a location of an alignment pattern located on amulti-layered printed circuit board substrate, said alignment patternhaving a known orientation to said second electrical circuit pattern;and an electrical circuit pattern generator recording an electricalcircuit pattern on said upper surface in a desired orientation withreference to the alignment pattern.
 43. Apparatus for recording anelectrical circuit pattern according to claim 42, and wherein saidalignment pattern is disposed along said upper layer.
 44. Apparatus forrecording an electrical circuit pattern according to claim 43, andwherein said alignment pattern is defined by a plurality of holes insaid upper surface.
 45. Apparatus for recording an electrical circuitpattern according to claim 44, and wherein said plurality of holes isarranged in a non-periodic pattern.
 46. Apparatus for recording anelectrical circuit pattern according to claim 44, and wherein saidplurality of holes do not pass through said lower layer.
 47. Apparatusfor recording an electrical circuit pattern according to claim 42, andwherein said alignment pattern is defined by a plurality of holesthrough said multi-layered printed circuit board substrate. 48.Apparatus for recording an electrical circuit pattern according to claim47, and wherein said plurality of holes is arranged in a non-periodicpattern.
 49. Apparatus for recording an electrical circuit patternaccording to claim 42, and wherein said alignment pattern is defined bya plurality of visible objects deposited on said upper surface, saidvisible objects being arranged in a non-periodic pattern.
 50. Apparatusfor recording an electrical circuit pattern according to claim 49, andwherein said plurality of visible objects is a plurality of markings.51. Apparatus for recording an electrical circuit pattern according toclaim 50, and wherein said markings are dimples.
 52. Apparatus forrecording an electrical circuit pattern according to claim 42, andwherein said an alignment pattern location sensor comprises a digitalcamera and image processing circuitry operative to acquire an image andcompute a location of said alignment pattern.
 53. Apparatus forrecording an electrical circuit pattern according to claim 52, andwherein said location of said alignment pattern is computed in acoordinate system employed by said electrical circuit pattern generator.54. Apparatus for recording an electrical circuit pattern according toclaim 53, and wherein said upper layer includes a photosensitizedsurface and said electrical circuit pattern generator is a laser directimaging scanner selectively recording an electrical circuit pattern onsaid photosensitized surface.
 55. Apparatus for recording an electricalcircuit pattern according to claim 53, and wherein said upper layerincludes a photosensitized surface and said electrical circuit patterngenerator comprises a phototool mask and a light projector projectinglight through said phototool mask onto said photosensitized surface toselectively record an electrical circuit pattern thereon.